Sequential Circuit
Q2.
The minimum number of JK flip-flops required to construct a synchronous counter with the count sequence (0,0,1,1,2,2,3,3,0,0,...) is __________ .Q3.
Consider a sequential digital circuit consisting of T flip-flops and D flip-flops as shown in the figure. CLKIN is the clock input to the circuit. At the beginning, Q1, Q2 and Q3 have values 0, 1 and 1, respectively.Which one of the given values of (Q1, Q2, Q3) can NEVER be obtained with this digital circuit?Q4.
A new flipflop with inputs X and Y, has the following property\begin{array}{|c|c|c|c|} \hline \mathbf{X} & \mathbf{Y} & \text { Current state } & \text { Next state } \\ \hline 0 & 0 & Q & 1 \\ 0 & 1 & Q & \bar{Q} \\ 1 & 1 & Q & 0 \\ 1 & 0 & Q & Q \\ \hline \end{array}Which of the following expresses the next state in terms of X,Y, current state?Q7.
The next state table of a 2-bit saturating up-counter is given below. \begin{matrix} Q_{1} & Q_{0} & Q_{1}^{+} &Q_{0}^{+} \\ 0 & 0 & 0 & 1 \\ 0 & 1 & 1 & 0\\ 1 & 0 & 1 & 1\\ 1 & 1 & 1 & 1 \end{matrix} The counter is built as a synchronous sequential circuit using T flip-flops. The expression for T_1 \; and \; T_0 areQ8.
Consider a combination of T and D flip-flops connected as shown below. The output of the D flip-flop is connected to the input of the T flip-flop and the output of the T flip-flop is connected to the input of the D flip-flop Initailly, both Q_{0} and Q_{1} are set to 1 (before the 1st clock cycle). The outputsQ9.
We want to design a synchronous counter that counts these quence 0-1-0-2-0-3 and then repeats. The minimum number of J-K flip flop srequired to implement this counteris ________.Q10.
Consider the sequential circuit shown in the figure, where both flip-flops used are positive edge-triggered D flip-flops. The number of states in the state transition diagram of this circuit that have a transition back to the same state on some value of "in" is _____.